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november 2001 advance information copyright ? alliance semiconductor. all rights reserved. as6yb51216 1.65v to 2.2v 512k 16 intelliwatt? super low-power cmos sram 11/1/01; v.0.9.8 alliance semiconductor p. 1 of 11 ? as6yb51216 intelliwatt? active power circuitry industrial temperature range (-40 o - +85 o c) organization: 524,288 words x 16 bits 1.65v to 2.2v power supply range fast access time of 70 ns low power consumption: active - 33 mw max at 2.2 v and 70 ns low power consumption: standby - 33 w max at 2.2v 1.0v data retention equal access and cycle times easy memory expansion with cs 1, cs2, oe inputs smallest footprint package - 48-ball fbga; 7.0 x 9.0 mm esd protection 2000 volts latch-up current 200 ma logic block diagram 512k 16 array (8,388,608) oe cs 1 we column decoder row decoder a0~a8 v dd v ss control circuit i/o1?i/o8 i/o9?i/o16 ub lb i/o buffer cs2 a9~a18 bbbbbbbb pin arrangement (top view) 48-csp ball-grid-array package 123456 alb oe a0 a1 a2 cs2 bi/o9ub a3 a4 cs 1i/o1 c i/o10 i/o11 a5 a6 i/o2 i/o3 dv ss i/o12 a17 a7 i/o4 v cc ev cc i/o13 v ss a16 i/o5 v ss f i/o15 i/o14 a14 a15 i/o6 i/o7 g i/o16 dnu a12 a13 we i/o8 h a18 a8 a9 a10 a11 dnu note: dnu = do not use selection guide product v cc range speed (ns) power dissipation min (v) ty p (v) max (v) operating (i cc1 ) standby (i sb1 ) max (ma) max ( a) as6yb51216 1.65 1.8 2.2 70/85 2 15 features
11/1/01; v.0.9.8 alliance semiconductor p. 2 of 11 as6yb51216 functional description the as6yb51216 is a low-power cmos 8,388,608-bit static ra ndom access memory (sram) device organized as 524,288 words x 16 bits. it is designed for memory applications where sl ow data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 70/85 ns are ideal for low-power applications. active high and low chip enables (cs 1 and cs2) permit easy memory expansion with multiple-bank memory systems. when cs 1 is high or cs2 is low, or ub and lb are high, the device enters standby mode. the as6yb51216 is guaranteed not to exceed 33 w at 2.2v. the device also retains data when v cc is reduced to 1.0v for even lower power consumption. the device can also be put into standby mode when deselected (cs 1 is high or cs2 is low). the input/output pins (i/o0 through i/o15) are placed in a high-impedance state when deselected ( cs 1 is high or cs2 is low), outputs are disabled (oe high), ub and lb are disabled (ub , lb high), or during a write operation ( cs 1 is low or cs2 is high and we low). writing to the device is accomplished by taking chip enables cs 1 low, cs2 high and write enable (we ) input low. if byte low enable (lb ) is low, then data from i/o pins (i/o0 through i/o7), is written into the location spec ified on the address pins (a0 through a18). if byte high enable (ub ) is low, then data from i/o pins (i/o8 through i/o15) is written into the location spec ified on the address pins (a0 through a18). to avoid bus cont ention, external devices should drive i/o pins only after out- puts have been disabled with output enable (oe ) or write enable (we ). reading from the device is accomplished by taking chip enable cs 1 low, cs2 high and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (lb ) is low, then data from the memory location specified by the address pins will appear on i/o0 to i/o7. if byte high enable (ub ) is low, then data from memory will appear on i/o8 to i/o15. these devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1?i /o8, and ub controls the higher bits, i/o9?i/o16. all chip inputs and outputs are cm os-compatible, and operation is from a single 1. 65v to 2.2v supply. device is available in th e jedec 48-ball fbga packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions outside thos e indicated in the operational sections of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings parameter symbol min max unit vo l t ag e o n v cc relative to v ss v tin ?0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o ?0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c temperature with v cc applied t bias ?55 +125 c dc output current (low) i out ?20ma
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 3 of 11 truth table cs 1 cs2 we oe lb ub supply current i/o1?i/o8 i/o9?i/o16 mode hxx x x x i sb high z high z standby (i sb ) xlxx x x xxxx h h lhhh l x i cc high z high z output disable (i cc ) lhhh x l lhhl lh i cc d out high z read (i cc ) hl high zd out ll d out d out lhl x lh i cc d in high z write (i cc ) hl high zd in ll d in d in key: x = don?t care, l = low, h = high.recommended operating condition (over the operating range) dc recommended operating condit ion (over the operating range) parameter description test conditions min max unit vcc supply voltage - - 1.65 2.2 v v oh output high voltage i oh = ?0.1ma v cc = 1.65v 1.4 v v ol output low voltage i ol = 0.1ma v cc = 1.65v 0.2 v v ih input high voltage v cc = 2.2v 1.4 v cc + 0.2 v v il input low voltage v cc = 1.65v ?0.2 0.4 v i ix input load current gnd < v in < v cc ?1 +1 a i oz output load current gnd < v o < v cc; outputs high z ?1 +1 a i cc v cc operating supply current i out = 0ma, f = 0 v cc = 2.2v 1ma i cc1 @ 1mhz average v cc operating supply current at 1 mhz i out = 0ma, f =1mhz v cc = 2.2v 2 ma i cc2 average v cc operating supply current i out = 0ma, f = f max v cc = 2.2v 15 ma at 70ns ma 10 ma at 85ns i sb cs power down current; ttl inputs cs1 > v cc ? 0.2v or cs2< 0.2v or ub = lb > v ih , other inputs = v il or v ih , f = 0 v cc = 2.2v 100 a i sb1 cs power down current; cmos inputs cs1 > v cc ? 0.2v or cs2< 0.2v ub = lb > v cc ? 0.2v other inputs = 0v ? v cc , f = f max v cc = 2.2v 15 a
11/1/01; v.0.9.8 alliance semiconductor p. 4 of 11 as6yb51216 key to switching waveforms read waveform 1 (address controlled) capacitance (f = 1 mhz, t a = room temperature, v cc = nominal) parameter symbol signals test conditions max unit input capacitance c in a, cs 1, cs2, we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf read cycle (over the operating range) parameter symbol ?70/85 unit notes min max read cycle time t rc 70/85 ? ns address access time t aa ? 70/85 ns 3 chip select to output access time t acs ? 70/85 ns 3 output enable (oe ) access time t oe ? 35/40 ns output hold from address change t oh 10 ? ns 5 chip select o low z output t clz 10 ? ns 4, 5 chip disable to high z output t chz ?20ns 4, 5 oe low to low z output t olz 5 ? ns 4, 5 ub /lb access time t ba ? 70/85 ns ub /lb low to low z t blz 10 ? ns 4, 5 ub /lb high to high z t bhz ?20ns 4, 5 oe high to output in high z t ohz ?20ns 4, 5 power up time t pu 0 ? ns 4, 5 power down time t pd ?55ns 4, 5 undefined/don?t care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 5 of 11 read waveform 2 (cs 1, cs2, oe , ub , lb controlled) write cycle (over the operating range) parameter symbol ?70/85 unit notes min max write cycle time t wc 70/85 ? ns chip enable to write end t cw 60/70 ? ns 12 address setup to write end t aw 60/70 ? ns address setup time t as 0?ns12 write pulse width t wp 50/60 ? ns write recovery time t wr 0?ns address hold from end of write t ah 0?ns data valid to write end t dw 30/35 ? ns data hold time t dh 0 ? ns 4, 5 write enable to output in high z t wz ?20ns4, 5 output active from write end t ow 5 ? ns 4, 5 ub /lb low to end of write t bw 60/70 ? ns data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t acs t lz address oe cs 1 lb , ub d out cs 2
11/1/01; v.0.9.8 alliance semiconductor p. 6 of 11 as6yb51216 write waveform 1 (we controlled)
write waveform 2 (cs 1controlled)
address cs 1 lb , ub we d in d out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid cs2 t wr address cs 1 lb , ub we d in t wc t cw t bw t wp t dw t dh t ow t wz t ah d out data undefined high z high z t as t aw data valid t clz cs2 t wr
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 7 of 11 write waveform 3 (lb , ub controlled) address cs 1 lb , ub we d in t wc t cw t bw t wp t dw t dh t ah d out high z high z t as t aw data valid cs2 t wr
11/1/01; v.0.9.8 alliance semiconductor p. 8 of 11 as6yb51216 data retention waveform data retention characteristics (over the operating range) parameter symbol test conditions min max unit v cc for data retention v dr v cc = 1.0v chip select controlled a b or lb / ub controlled c v in v cc ? 0.2v or v in 0.2v : cs 1 controlled: cs 1 vcc-0.2v; cs2 0.2v cs2 controlled: cs2 0.2v : lb / ub controlled: lb = ub

1.0v 2.2 v data retention current i ccdr ?8 a chip deselect to data retention time t cdr 0?ns operation recovery time t r t rc ?ns cs 1, t cdr data retention mode cs 1 controlled lb /ub gnd v cc 1.65v 1.4v v dr t r cs 1 vcc -0.2, lb = ub vcc -0.2v t cdr data retention mode cs 2 controlled gnd v cc 1.65v v dr 0.4v t r cs2 0.2v cs2
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 9 of 11 ac test loads and waveforms notes 1during v cc power-up, a pull-up resistor to v cc on cs is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs 1 and oe are low for read cycle. 8 address valid prior to or coincident with cs 1 transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs 1 or we must be high during addr ess transitions. either cs 1 or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 n/a. 13 1.0v data retention applies indu strial temperature range operations. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. parameters v cc = 1.8v unit r1 13500 ohms r2 10800 ohms r th 6000 ohms v th 0.8v volts v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc typ < 5 ns (c) thevenin equivalent: output r th v including jig and scope
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 10 of 11 package diagrams and dimensions minimum ty p i c a l maximum a ? 0.75 ? b 6.90 7.00 7.10 b1 ? 3.75 ? c8.49.08.6 c1 ? 5.25 ? d 0.30 0.35 0.40 e??1.20 e1 ? 0.68 ? e2 0.22 0.25 0.27 y??0.08 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 65432 1 48-ball fbga bottom view to p vi ew a b c d e f g h ball #a1 ball #a1 index c1 a a b1 b elastomer c sram die side view detail view die die a e2 e y 0.3/typ 1 2 d
as6yb51216 11/1/01; v.0.9.8 alliance semiconductor p. 11 of 11 ? copyright alliance semiconductor corporation. all rights re served. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all o ther brand and product names may be the trademarks of their respective companies. alliance re serves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for an y errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these spec ifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and user s, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any respon sibility or liability arising out of the application or use of any product described herein , and disclaims any express or implied warranties related to the sale and/or use of alliance products including liab ility or warranties related to fitness for a particular purpo se, merchantability, or infringement of any intellectua l property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of allian ce products are made exclusivel y according to alliance's terms and conditions of sa le. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks , or any other intellectual property rights of alliance or third parties. alliance does not authori ze its products for use as critical components in life- supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and t he inclusion of alliance products in such life-su pporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alli ance against all claims arising from such use. ordering codes speed (ns) ordering code package type operating range 70 as6yb51216-70bi 48-ball fine pitch bga industrial 85 as6yb51216-85bi 48-ball fine pitch bga industrial 70 as6yb51216-70bc 48-ball fine pitch bga commercial 85 AS6YB51216-85BC 48-ball fine pitch bga commercial part numbering system as6ya 51216 b c ori sram intelliwatt? prefix device number package: b: csp / bga temperature range: c: commercial: 0 c to 70 c i: industrial: ?40 c to 85 c

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